//////////////////////////////////////////////////////////////////////////////
// project: uart for up_link and down_link
// name: 	uart
// designer:wanggj 
// data:	2014_06_01
// description:
//			1 byte to tx and rx once 
//			din which to tx should be set before or at the same clk when en_tx enable,
//			and then set en_tx "1" to start tx
//			when tx end ,tdc will send 1 pulse
//			when rx end ,rdc will send 1 pulse
//			if rx faill ,error will be "1"
//			clk is 50MHz
//			baud_set: "1" -> 115200 bps "0" -> 19200 bps
/////////////////////////////////////////////////////////////////////////////////
module uart(	clk,
				nrst,
				en_tx,			//start to tx
				rxd,
				din,			//data which used to tx
				baud_set,		//set baud
				//out
				txd,
				error,
				rdc,			//rx data completed
				tdc,			//tx data completed
				data			//receive data from rx
				//test
				//ledtx,
				//ledrx
				);
input 			clk,
				nrst,
				en_tx,
				rxd,
				baud_set;
input[7:0] 		din;

output 			txd,
				error,
				rdc,
				tdc;
output[7:0] 	data;
//output 		ledrx,ledtx;
//reg   		ledrx,ledtx;
//reg			en_tx;

//wire [7:0]		data;
//test
//reg ledrx,ledtx;

// always@(posedge clk or negedge nrst)
// if(!nrst)
	// begin
 // ledrx <= 0;
 // ledtx <= 0;
 // en_tx <= 0;
 // end
 // else
	// begin
	// if(rdc) begin ledrx <= ledrx + 1; en_tx <= 1;end
	// else en_tx <= 0;
	// if(tdc) ledtx <= ledtx + 1;
	// end
	
reg[1:0]  rxd_r;

always @(posedge clk)
	if(~nrst)
		rxd_r <= 2'b11;
	else
		rxd_r <= {rxd_r[0], rxd};

uart_rx u1(		.clk(clk),
				.nrst(nrst),
				.rxd(rxd_r[1]),
				.baud_set(baud_set),
				//out
				.error(error),
				.rdc(rdc),
				.data(data));
				
uart_tx u2(		.clk(clk),
				.nreset(nrst),
				.en_tx(en_tx),
				.baud_set(baud_set),
				.din(din),
				//out
				.tdc(tdc),
				.txd(txd)
				);
endmodule 
